ispLSI3256芯片破解

0 次 时间：2009-08-27 / 10:41:26 来源：夏生

ispLSI3256 Features：

• HIGH-DENSITY PROGRAMMABLE LOGIC
— 128 I/O Pins
— 11000 PLD Gates
— 384 Registers
— High Speed Global Interconnect
— Wide Input Gating for Fast Counters, State
Machines, Address Decoders, etc.
— Small Logic Block Size for Random Logic
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY
— fmax = 77 MHz Maximum Operating Frequency
— tpd = 15 ns Propagation Delay
— TTL Compatible Inputs and Outputs
— Electrically Erasable and Reprogrammable
— Non-Volatile
— 100% Tested at Time of Manufacture
— Unused Product Term Shutdown Saves Power
• IN-SYSTEM PROGRAMMABLE
— In-System Programmable™ (ISP™) 5-Volt Only
— Increased Manufacturing Yields, Reduced Time-to-
Market, and Improved Product Quality
— Reprogram Soldered Devices for Faster Debugging
• 100% IEEE 1149.1 BOUNDARY SCAN COMPATIBLE
• OFFERS THE EASE OF USE AND FAST SYSTEM
SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY
OF FIELD PROGRAMMABLE GATE ARRAYS
— Complete Programmable Device Can Combine Glue
Logic and Structured Designs
— Five Dedicated Clock Input Pins
— Synchronous and Asynchronous Clocks
— Programmable Output Slew Rate Control to Minimize
Switching Noise
— Flexible Pin Placement
— Optimized Global Routing Pool Provides Global
Interconnectivity
• ispDesignEXPERT™ – LOGIC COMPILER AND COMPLETE
ISP DEVICE DESIGN SYSTEMS FROM HDL
SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING
— Superior Quality of Results
— Tightly Integrated with Leading CAE Vendor Tools
— Productivity Enhancing Timing Analyzer, Explore
Tools, Timing Simulator and ispANALYZER™
— PC and UNIX Platforms

ispLSI3256 Description：

The ispLSI 3256 is a High Density Programmable Logic
Devices containing 384 Registers, 128 Universal I/O
pins, five Dedicated Clock Input Pins, eight Output Routing
Pools (ORP), and a Global Routing Pool (GRP) which
allows complete inter-connectivity between all of these
elements. The ispLSI 3256 features 5-Volt in-system
programmability and in-system diagnostic capabilities.
The ispLSI 3256 offers non-volatile reprogrammability of
the logic, as well as the interconnect to provide truly
reconfigurable systems.
The basic unit of logic on the ispLSI 3256 device is the
Twin Generic Logic Block (Twin GLB) labelled A0, A1...H3.
There are a total of 32 of these Twin GLBs in the ispLSI
device. Each Twin GLB has 24 inputs, a programmable
AND array and two OR/Exclusive-OR Arrays, and eight
outputs which can be configured to be either combinatorial
or registered. All Twin GLB inputs come from the
GRP.