XC95144XV芯片破解

1 次 时间：2009-08-26 / 11:46:24 来源：夏生

XC95144XV  Features：

• 144 macrocells with 3,200 usable gates
• Available in small footprint packages
- 100-pin TQFP (81 user I/O pins)
- 144-pin TQFP (117 user I/O pins)
- 144-pin CSP (117 user I/O pins)
• Optimized for high-performance 2.5V systems
- Low power operation
- Multi-voltage operation
• Advanced system features
- In-system programmable
- Two separate output banks
- Superior pin-locking and routability with
FastCONNECT II™ switch matrix
- Extra wide 54-input Function Blocks
- Up to 90 product-terms per macrocell with
individual product-term allocation
- Local clock inversion with three global and one
product-term clocks
- Individual output enable per output pin
- Input hysteresis on all user and boundary-scan pin
inputs
- Bus-hold ciruitry on all user pin inputs
- Full IEEE Standard 1149.1 boundary-scan (JTAG)
• Fast concurrent programming
• Slew rate control on individual outputs
• Enhanced data security features
• Excellent quality and reliability
- Endurance exceeding 10,000 program/erase
cycles
- 20 year data retention
- ESD protection exceeding 2,000V
业务热线：  
解密热线：130 6693 6900
业务QQ：1994 226
地址：广东省深圳市福田区华强北振兴路格林网苑1707室
业务邮箱：1994 226@qq.com

邮编：518000
传真：

详细介绍请参考：
 Xilinx  XC95144XV技术手册：XC95144XV.PDF